In recent years, there has been an increased interest in asynchronous logic circuits. This increased interest is attributable to the fact that asynchronous logic circuits are able to operate at particularly fast speed, much faster, for example, than equivalent clocked circuits and require fewer signal interconnections. Within the communication processing arts, asynchronous logic circuits known as self-clocking have been described which encode the transmitted data sequences in ways which inherently embed clock energy within the encoded signal's frequency spectrum. This embedded clock energy is typically extracted at the receiver and used to regenerate a local copy of the synchronous data clock for sampling and processing of the received bit patterns.
Prior art such as U.S. Pat. No. 3,828,167 by Goldfarb, describes encoding techniques which vary the pulse width of a binary-1 versus that of a binary-0 in order to allow the receiver to discriminate between the two values by measuring the pulse width relative to a clock reference located at the receiver. This technique has the drawback of being slower to transmit than those that employ symmetrical bit intervals for both binary values. Other prior art, such as the IEEE 802 Local Area Network standards, employ Manchester encoding or 4B5B encoding to create self-clocking data. The latter is a technique where binary characters of some fixed bit length, are encoded into a second binary sequence, comprising a number of bits greater than that of the source characters. The larger sequence utilizes only a subset of the binary codes possible with the larger number of bits. The code subset is chosen to preserve and intensify clock frequency energy to the receiving clock recovery circuit while maintaining long term energy balance to minimize DC offset in the signal. Commercially available circuits of this type presently operate at serial data rates up to several giga-bits per second. However, there are several drawbacks to these prior art approaches. These techniques do not provide a definitive clock edge in their encoding for of every bit interval. For techniques that embed clock energy with extra bit codes, they typically suffer from the inclusion of a relatively large percentage of extra overhead bits. Clock recovery circuits utilized with these techniques often employ phase lock loop (PLL) circuits which must be implemented in some form of mixed signal technology if incorporated within an integrated circuit (IC). Such an approach usually results in increased design complexity and manufacturing expense of the receiver along with inherent restrictions on the number of simultaneous receivers in a single IC package due to crosstalk and noise sensitivity of PLL circuits within the IC.
The prior art in the data processing related applications have centered on asynchronous circuits know as self-timed circuits used for the purpose of data transfer. Some instances of prior art in self-timed circuits use a bi-directional signaling protocol, comprised of the transmit and receive circuits exchanging a request and acknowledgment signals respectively, to complete a data transfer. In the prior art of U.S. Pat. No. 5,386,585 by Traylor, a data transfer protocol is described which utilizes a data request issued by the transmitter and a Ready signal from the receiver to perform the handshaking, in much the same manner as performed in earlier asynchronous FIFO circuits. These forms of bi-directional "Request & Acknowledgment" protocols are adequate for fast communication within a single integrated circuit device because of the small physical geometry which result in short signal transit times However, these "Request & Acknowledgment" protocols do not facilitate fast communication between modules when the signal transit delay between the modules may be several nanoseconds due to the relative physical proximity between transmitter and receiver being measured in meters.
Another prior art form of asynchronous data transfer employs dual-rail transition encoding as described by a technical paper by Ebergen, Segers, and Benko entitled Parallel Program and Asynchronous Circuit Design. This paper was included as a chapter in the book titled "Asynchronous Digital Circuit Design", starting at page 59. The book was authored by Birtwistle & Davis and published in 1995. With this method, each bit is implemented using two wires, one wire for the value zero and one wire for the value one. Sending a transition along the `0` wire implements the communication of a zero, and sending a transition along the `1` wire implements the communication of a one. Each transition is non-overlapping with other pulses on the same wire or with transitions on the other wire. The requirement for non-overlapping pulses means that dead time must be inserted between pulses. This dead time reduces or limits the maximum speed of data transmission to values less than could be possible if the pulses could overlap or be adjacent.
As will be described the present invention departs from the strategy of requiring the receiver to regenerate a local copy of the data clock or deliver a data transfer acknowledgment signal. The invention also departs from the practice of adding extra bits to the data to facilitate clock recovery.